Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its stored data for some extended period without the application of power. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR Flash and NAND Flash. The designation is derived from the logic used to read the devices. FIG. 1 illustrates a NAND type flash memory array architecture 100 wherein the floating gate memory cells 102 of the memory array are logically arranged in an array of rows and columns. In a conventional NAND Flash architecture, “rows” refers to memory cells having commonly coupled control gates, while “columns” refers to memory cells coupled as one or more NAND strings of memory cells 108, for example. The memory cells 102 of the array are arranged together in strings (e.g., NAND strings), typically of 8, 16, 32, or more each. Memory cells of a string are connected together in series, source to drain, between a source line 114 and a data line 116, often referred to as a bit line. Each series string of memory cells is coupled to source line 114 by a source select gate such as select gate 110 and to an individual bit line 116 by a drain select gate 104, for example. The source select gates, such as 110, are controlled by a source select gate (SGS) control line 112 coupled to their control gates. The drain select gates, such as 104, are controlled by a drain select gate (SGD) control line 106. The one or more strings of memory cells are also typically arranged in groups (e.g., blocks) in which the one or more strings coupled to multiple bit lines of a particular group are formed in a common semiconductor material (e.g., common semiconductor well, such as a common p-well) 138 formed in the substrate of the memory device. Due to this commonality of the p-well 138 between the one or more strings of memory cells, each p-well region near each of the memory cell strings has the same potential, such as 0V, or might be biased to a high voltage as part of an erase operation, for example.
The memory array is accessed by a string driver (not shown) configured to activate a logical row of memory cells by selecting a particular access line, often referred to as a word line, such as WL7-WL0 1187-0, for example. Each word line 118 is coupled to the control gates of a row of memory cells 120. Bit lines BL1-BL4 1161-1164 can be driven high or low depending on the type of operation being performed on the array. As is known to those skilled in the art, the number of word lines and bit lines might be much greater than those shown in FIG. 1.
Memory cells 102 can be configured as what are known in the art as Single Level Memory Cells (SLC) or Multilevel Memory Cells (MLC). SLC and MLC memory cells assign a data state (e.g., as represented by one or more bits) to a specific range of threshold voltages (Vt) stored on the memory cells. Single level memory cells (SLC) permit the storage of a single binary digit (e.g., bit) of data on each memory cell. Meanwhile, MLC technology permits the storage of two or more binary digits per cell (e.g., 2, 4, 8, 16 bits), depending on the quantity of Vt ranges assigned to the cell and the stability of the assigned Vt ranges during the lifetime operation of the memory cell. By way of example, one bit (e.g., 1 or 0) may be represented by two Vt ranges, two bits by four ranges, three bits by eight ranges, etc.
Programming typically involves applying one or more programming pulses to a selected word line and thus to the control gate of each memory cell coupled to the selected word line. Typical programming pulses start at or near 15V and tend to increase in magnitude during each programming pulse application. While the program voltage (e.g., programming pulse) is applied to the selected word line, a potential, such as a ground potential, is applied to the substrate, and thus to the channels of these memory cells, resulting in a charge transfer from the channel to the floating gates of memory cells targeted for programming. More specifically, the floating gates are typically charged through direct injection or Fowler-Nordheim tunneling of electrons from the channel to the floating gate, resulting in a Vt typically greater than zero in a programmed state, for example. In addition, an inhibit voltage is typically applied to bit lines not coupled to a NAND string containing a memory cell that is targeted for programming.
Memory cells 102 of a selected block are typically erased by first pre-programming all the memory cells of a selected block to bring the memory cells of the selected block to a more uniform state and to help reduce the possibility of overerasure. The memory cells are erased by driving the p-well 138, and thus the channel regions of the selected block, to an erase voltage, such as 25V, for example. The word lines 118 coupled to the block of memory cells are then typically driven to a lower voltage, such as 1.5V, for example. This applies an erase field across the memory cells sufficient to cause carriers stored in the floating gates and/or charge trapping layers to be removed and the memory cells placed in an erased state with an erased threshold level.
FIG. 2 shows a side view of a single string of memory cells 208, such as string 108 shown in FIG. 1, formed in a p-well 238 during an erase operation performed upon the string of memory cells. The control gates of each memory cell are shown coupled to the word lines 2180-7, such as word lines 1180-7 as shown in FIG. 1. A source select gate 210 and drain select gate 204 are also illustrated.
During a typical erase operation the p-well 238 is biased to a particular erase voltage, such as 25V, for example, to bias the channel regions of the memory cells. The word lines 218 are also biased to a particular bias level, such as 1.5V. The source select 212 and drain select 206 gate control lines are then left floating in order to disable the source select gate 210 and the drain select gate 204. Resulting from the 25V bias imposed on the p-well 238, the bit line 216 and the source line 214 associated with the NAND string 208 are also biased up to approximately 25V. The proximity of the floating SGS control line 212 to the source line 214 causes the floating SGS control signal line to be coupled up to a potential of approximately 20V, for example. A similar 20V bias condition exists on the floating SGD control line 206 as a result of the proximity to the bit line 216 biased to 25V. This 20V bias condition on the SGS control signal line 212 can cause a higher bias condition (e.g., 3V) to occur on the word line 2180 adjacent to the SGS control signal line. A similar effect occurs on the word line 2187 adjacent the SGD control signal line 206. The higher bias condition on word lines 2180 and 2187 (e.g., 3V versus 1.5V as shown in FIG. 2) can cause the memory cells coupled to those word lines to erase slower then word lines 2182-6, for example. This can result in a particular NAND string of memory cells requiring additional time to complete an erase operation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present disclosure, there is a need in the art for alternate erase operations for memory devices.